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ADN2811,pdf,datasheet

 Dual Rate Limiting Amplifier and Clock a
  • 软件大小:296KB
  • 更新日期:2009/9/19
  • 软件语言:简体中文
  • 软件类别:机械电子
  • 软件授权:共享软件
  • 软件官网:
  • 适用平台:Vista, Win2003, WinXP, Win2000, NT

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    TheADN2811providesreceiverfunctionsofQua。

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    The ADN2811 provides receiver functions of Quantization, Signal Level Detect and Clock and Data Recovery at rates of OC-48 and the associated FEC rates. All SONET jitter requirements are met, including: Jitter Transfer; Jitter Generation; and Jitter Tolerance. All specifications are quoted for -40ºC to +85ºC ambient temperature unless otherwise noted.

    The proprietary delay and phase-locked loop design of the ADN2811 provides unprecedented jitter performance for robust high-speed networking designs.

    The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip crystal oscillator. Both native rates and 15/14 rate digital wrappers rates are supported by the ADN2811, without any change of reference clock required. This device together with a PIN diode and a TIA preamplifier can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold.

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